1. Field of the Invention:
The present invention relates to an IC memory card, and, more particularly, to an input/output circuit for a RAM card or the like which incorporates a data backup battery.
2. Description of the Related Art:
FIG. 1 is a block diagram of a conventional IC memory card which is described in "IC MEMORY CARD GUIDELINE" issued on September in 1986 by the Personal Computer Business Committee of the Japan Electrical Industry Development Association, and in particular shows the internal basic circuit of a RAM card. In FIG. 1, a RAM chip portion 2 generally includes a plurality of RAM chips (not shown). An interface connector 1, which connects the RAM card to an external circuit, is connected through a lower address bus 6 and a data bus 7 to individual RAM chips in the RAM chip portion 2. A chip select circuit 3 designed to select a specified RAM chip in the RAM chip portion 2 is connected to the interface connector 1 through a control bus 4 and an upper address bus 5. The chip select circuit 3 is also connected to the individual RAM chips in the RAM chip portion 2 through the control bus 4. An upper address represents an address used to determine which RAM chip in the RAM chip portion 2 is selected, and a lower address represents an address in each of the RAM chips. A power source control circuit 11 is connected via the interface connector 1 to an external power source (not shown) and the earth through an external power source line 8 indicated by a voltage Vcc and a grounding line 9 indicated by GND, respectively. The power source control circuit 11 is also connected through a power source line 10a indicated by a voltage Vbb to a date backup battery 10 (hereinafter referred to simply as a battery) incorporated in the RAM card to retain the data stored in the RAM chip portion 2 when the RAM card is disconnected from a personal computer or the like and no external power is supplied thereto. The power source control circuit 11 is also connected to the RAM chip portion 2 and the chip select circuit 3 through power source lines 11a to supply power thereto from the external power source or the battery 10. FIG. 1 does not refer to a practical situation, that is, it does not show a detailed circuit structure of the type required to cope with static electricity or other problems. In an actual circuit, however, a general-purpose gate IC (74HCXXX series) which resists static electricity relatively well is generally connected between the interface connector 1 and the RAM chip portion 2 in order to protect the RAM chip portion 2 which is vulnerable to disturbances such as static electricity. In particular, a general-purpose gate IC is inserted in the lower address bus 6 between the interface connector 1 and the RAM chip portion 2 because a signal on the lower address bus 6 is more vulnerable to static electricity than is a signal on the data bus 7.
FIG. 2 is a block diagram of parts of a conventional RAM card of FIG. 1, in which the same reference numerals are used to denote parts which are identical to those in FIG. 1. In the structure shown in FIG. 2, an input gate IC circuit 12, which is an input side gate circuit, is inserted in the lower address bus 6 to protect the RAM chip portion 2 against disturbances. The RAM chip portion 2 is connected between the external power source line 8 and the grounding line 9 and between the two ends of the battery 10 which supplies a 3 V of voltage for data backup. A pull-up resistor 13 for pulling up the voltage of the lower address bus 6 to the Vcc of the external power source line 8 is connected between the external power source line 6 and the lower address bus 6. A diode 14 is connected to the battery 10 to ensure that current does not flow backwards thereto. A level detection circuit 16 is designed to detect the voltage Vcc of the external power source line 8 and supply an ON(close)-signal to a transistor change-over switch 15 so that it closes when the voltage Vcc becomes about 4.4 V or above after the RAM card has been connected to a personal computer or the like (not shown) and the power has been turned on. The level detection circuit 16 creates an OFF(open)-signal so that the transistor change-over switch 15 opens when the voltage Vcc of the external power supply line 8 becomes 4.4 V or less after the power has been turned off. A control signal 16a is the signal for actuating this on-off control. The input gate IC circuit 12 improves the resistance of the RAM card to static electricity. IC circuit 12, by virtue of its signal amplification function, overcomes any problem that may occur involving a signal delay which depends on the storage capacity of the RAM chip portion 2 when the RAM chip portion 2 consists of a plurality of RAM chips. The level detection circuit 16 may be readily constructed by utilizing an IC which is available on the market under the name of reset IC. IT sends on ON(close)-signal to the transistor change-over switch 15 when the voltage Vcc of the external power source line 8 exceeds, for example, about 4.4 V, which is a value slightly higher than the lowest voltage at which the RAM chip portion 2 can operate normally. Circuit 16 thus enables data to be read out and written in the RAM chip portion 2 when the voltage Vcc is at a desired value or above.
FIG. 3 shows part of the pin layout of an IC chip frequently used as the input gate IC circuit 12 shown in FIG. 2, e.g., 74HC245. The pin arrangement includes a power source terminal 17, a grounding terminal 18, a data direction control input DIR terminal 19 and an output control input terminal 20. The data direction control input DIR terminal 19 and the output control input terminal 20 are connected to the grounding terminal 18. FIG. 4 shows a CMOS general-purpose logic gate, which is one of the inverter circuits provided at the input stage of the 74HC245 shown in FIG. 3. In this inverter circuit, a p-channel MOSFET 21 and an N-channel MOSFET 22 are connected in series. This inverter is provided for each signal line. That is, if the lower address line 6 is a signal line which transmits a 15-bit signal in parallel, the IC chip employs 15 inverters. Since either the upper half (the p-channel) or the lower half (the n-channel) is on all the time in this CMOS inverter circuit, d.c. current It (generally called through current) does not flow from the power source terminal 17 to the grounding terminal 18. When the input voltage Vin of the input gate IC circuit 12, i.e., the voltage of the lower address bus 6, is at 5 V, the p-channel MOSFET 21 is off while the n-channel MOSFET 22 is on. Further, when the input voltage of the lower address bus 6 is at 0 V, the MOSFET 21 is on, and the MOSFET 22 is off. In actual operation, however, both of the MOSFETs 21 and 22 are on for a short time during the input voltage waveform transition, and the through current as well as the load current flow in the inverter. FIG. 5 shows this effect. When the input voltage Vin gradually increases, as shown in FIG. 5(a), and the voltage V of the power source terminal 17 of the input gate IC circuit 12 is kept at 5 V, the through current It that flows between the power source terminal 17 and the ground terminal 18 of the input gate IC circuit 12 varies in the manner shown in FIG. 5 (b). The through current It is at a maximum when the input voltage Vin is about one-half the voltage V (which is 5 V) of the power source terminal 17. This through current It sometimes reaches several hundreds of .mu.A in one CMOS inverter, which is too high a value to be ignored if the 74HC245 incorporates a large number of inverters.
While the RAM card is being carried from one place to another, a voltage is supplied to the RAM chip portion 2 from the battery 10 to retain the data stored therein. At this time, there is no voltage supply from the external power source line 8, and the transistor change-over switch 15 remains off while the address signal on the lower address bus 6 is at 0 V. When the RAM card is inserted in a personal computer or in a reader/writer for the IC memory card to allow data to be written in or data to be read from the RAM chip portion 2, a voltage is supplied from the external power source line 8, and data is accessed on the basis of address information. At this time, about 3 V has been already applied from the battery 10 to the power source terminal 17 of the input gate IC circuit 12, and the phenomenon illustrated in FIG. 5 occurs in the RAM card when either the voltage of the external power source line 8 or that of the lower address line 6 increases from 0 V to 5 V. In other words, when either the voltage of the external power source line 8 or that of the lower address line 6 is one-half that of the battery voltage, which is 3 V, the through current It flows in each of the inverters in the input gate IC circuit 12. It is the battery 10 which supplies this through current It, because the transistor change-over switch 15 is still off when the voltage of the external power source line is at 3/2 V. Further, the same phenomenon occurs when the external power source is turned off.
In the conventional RAM card arranged in the manner described above, each time the power is turned on and off after the card has been inserted into a personal computer or the like, excessive through current flows from the battery, consuming a great deal of power from battery and thereby decreasing the life of the battery.